Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLS, RAM, processors, and so forth).
An FPGA is typically implemented as an array of “hardware tiles”, with each hardware tile including one logic block (e.g., a CLB, a RAM block, or an IOB) plus the associated routing. Thus, each hardware tile includes both programmable logic and a portion of the programmable interconnect structure. Interconnect lines included in each hardware tile typically connect to interconnect lines in adjacent hardware tiles by abutment. Interconnections among the interconnect lines, and between the interconnect lines and the logic blocks, are made using programmable structures known as “switch matrices”. Switch matrices provide interconnections between physical elements by activating “programmable interconnect points”, or PIPS. Hardware tiles, switch matrices, and PIPs are well known in the arts of FPGA design and software representation.
The hardware tiles are typically programmed by loading a stream of configuration data (“bitstream”) into internal configuration memory cells that define how the logic blocks and interconnect structure are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
As previously described, advanced FPGAs can include logic blocks other than the typical CLBs and IOBs. For example, the Xilinx Virtex-II Pro™ FPGA includes blocks of Random Access Memory (RAM), blocks implementing multiplier functions, and embedded processor blocks. (The Xilinx Virtex-II Pro FPGA is described in detail in pages 19–71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.)
Configuration bitstreams are typically generated using “place-and-route” software. Place-and-route software accepts a user circuit description (e.g., in netlist form), partitions the user circuit into units that fit within the available logic blocks (partitioning), maps the units to the available logic blocks (mapping), assigns positions to the mapped logic blocks within the hardware tile array (placement), and determines acceptable routes for signals interconnecting the placed blocks (routing). A bitstream is then generated that represents the placed and routed design, such that loading the bitstream into the device implements the user design in the device.
To adequately perform the partitioning, mapping, placement, and routing functions, the FPGA implementation software must have access to an accurate representation of each of the configurable resources available in the FPGA. Traditionally, this information is stored in a variety of “software tiles”, one software tile being provided for each different hardware tile available on the FPGA. For example, separate software tiles are supplied for each of the CLB tiles, IOB tiles, RAM tiles, multiplier tiles, and processor tiles in the Xilinx Virtex-II Pro FPGA. There can also be multiple software tiles for a single type of logic block, with each software tile representing a different hardware tile. For example, one software tile can represent a CLB tile encapsulated by other CLB tiles, while another software tile represents a CLB on the outer edge of an array of CLBS.
FPGAs have been increasing in size and complexity with each product generation. Some currently available FPGAs require bitstreams including several million configuration bits. Clearly, both to reduce data storage needs and to simplify the place-and-route software, it is desirable to simplify as much as possible the software tiles used to represent the various hardware tiles. One known method of simplifying the software tiles is to create separate representations for certain basic elements that are often repeated in the various tiles, e.g., PIPs. These representations can then be referenced by more than one software tile rather than being completely respecified each time they are used. However, the correspondence between hardware tiles and software tiles is maintained by known software representations, regardless of the hierarchical nature of the software tile.
Clearly, it is desirable to further simplify PLD software representations, preferably using methods that also simplify the functionality of the PLD place-and-route software.